The invention is directed generally to improvements in semiconductor memories, and particularly to a system for improving the speed with which data is transferred to and from memory locations.
In computer systems and the like, it is frequently desired to rapidly read data stored in a number of successive memory locations. In such circumstances, an individual row and column address is not required for accessing the data in each location. All that is needed is the address of the first memory location and some means for automatically indexing the memory to the following successive locations. Rapid writing of data into successive memory locations may be achieved in the same general manner.
Some conventional memories incorporate a feature referred to as "page mode" operation for rapidly reading the data stored in successive memory locations. In this mode of operation, the data in one row of the memory is latched in a plurality of sense amplifiers. Then successive column addresses are input to the memory to successively output the data stored in each sense amplifier. Because successive row addresses are not required to read the data in each successive location in the accessed row, a two-to-one time savings is achieved in reading data. However, the ratio of a standard read-write cycle time to page mode cycle time (typically a factor of two) is frequently not large enough to warrant the added system complexity required to implement page mode operation. The present invention overcomes this problem by providing a much faster rate of data read and write.